1. Field of the Invention
The present invention relates to a digital image signal playback circuit in a digital image apparatus. More particularly, the invention relates to a digital image signal playback circuit which converts serial data, that is, image information transmitted in two channels of a digital image signal playback apparatus in a digital video tape recorder (hereinafter referred to as a VTR), into parallel data, corrects time base errors of the parallel data, and then reproduces the corrected data into a single channel.
2. Background Information
In a conventional digital image signal playback apparatus of a digital VTR, as shown in FIG. 1, serial data (image information) which is reproduced by a video tape head, inputted to the first and second channels I and II and then converted to parallel data in first and second serial-to-parallel conversion portions 1. First and second time base error correctors (hereinafter referred to as TBCs) in block 2 correct time base errors of the parallel data occurring during recording and reproducing. First and second sync detectors in block 3 detect a synchronizing signal included in the data outputted from the TBCs 2. The data outputted from the sync detectors 3 are supplied to first and second inner error correction decoders 4 which detect the original signal by means of parity data inserted in a symbol string of an error-created signal. The first and second correction decoders 4 then feed the signal into first and second deshuffling portions 5.
The deshuffling portions 5 write data from left to right, arranging the data from top to bottom in a matrix form, and read the data vertically to supply the data to multiplexer 6. Outer error correction decoder 7 then corrects the data errors which are transmitted by the multiplexer 6 to generate the error-corrected output data.
The conventional digital image signal playback circuit described above has a disadvantage, however, in that a large amount of hardware is required due to the complicated circuit construction of the sync detectors and inner error correction decoders which process a signal in two channels.
Another conventional digital playback circuit of a composite image signal is disclosed in Japanese patent laid-open publication No. 62-13195. This apparatus also has a disadvantage, however, in that a large mount of hardware is required since, after correcting a composite image signal input into a digital image signal output, the apparatus separates the digital signal into three chrominance signals R, G and B, and then records and reproduces them in three channels.